A frequency synthesizer is an apparatus which generates an output signal having a frequency which is an exact multiple of a reference frequency. The accuracy of the output signal frequency is typically determined by the accuracy and stability of the reference frequency source.
A common type of frequency synthesizer uses a phase-locked loop (PLL) to provide an output signal having a selectable, precise and stable frequency. The PLL includes a phase detector, a voltage-controlled oscillator (VCO) and, a feedback path arranged so that the phase of the VCO output is forced to be synchronous with the phase of the input reference frequency.
By using a divider circuit in the VCO feedback path and selectably controlling the division ratio, a variable frequency can be provided at the output of the frequency synthesizer. In this manner, the VCO output frequency is divided by the selectable divisor, and the VCO output frequency is an exact multiple of the reference frequency. If the divisor N is an integer, the smallest increment in the VCO output frequency value is necessarily equal to the magnitude of the reference frequency itself.
Accordingly, in order to provide a frequency synthesizer having a small step size between adjacent output frequencies, a very low reference frequency is required. Using a very low reference frequency, however, limits the frequency range and extends the time required for the PLL to settle (or lock) once a new frequency has been selected.
A common technique used to synthesize output signals having a frequency which is a rational multiple of the reference signal frequency is referred to as fractional-N synthesis. Typically, frequency divider circuits are implemented, so that they only divide by an integer value and it is necessary to simulate fractional division by changing the divisor integer value temporarily during the division process. This type of method, which is exemplified in U.S. Pat. No. 3,928,813 (Smith), incorporated herein by reference, requires significant additional circuitry for the fractional-division simulation and is, therefore, expensive to implement.
Other techniques used to synthesize output signals having a frequency which is a non-integer multiple of the reference signal frequency are referred to in U.S Pat. Nos. 4,068,199 (Madoff), 4,543,542 (Owen), 4,546,331 (DaSilva et al.), 4,800,342 (Jackson), 4,810,977 (Flugstad et al.), 4,816,774 (Martin), 4,833,425 (Culican, Sr. et al.), 4,994,768 (Shepherd et al.), 5,021,754 (Shepherd et al.), 5,038,117 (Miller), 5,038,120 (Wheatley et al.), 5,070,310 (Hietala et al.), 5,079,519 (Ashby et al.), 5,093,632 (Hietala et al.), and 5,111,162 (Hietala et al.), 5,166,642 (Hietala), all of which are herein incorporated by reference.
Another problem common to many of the known synthesizer PLL circuits is that they fail to provide an accurate and practicable way of frequency modulating the carrier injection signal for the radio transmitter. Previous efforts to achieve this end have resulted in essentially two sections of circuitry, one section using a PLL for narrow band frequency adjustment and another section for wideband frequency modulating a PLL output or input signal before the power amplifier of the radio transmitter. Such circuitry is duplicative and relatively expensive to implement in terms of both power and silicon space.
Accordingly, there is a need for a technique of frequency synthesis using fractional-N division which overcomes these deficiencies of the prior art. This need is especially prevalent in radio applications requiring frequency modulation in relatively narrow bands, for example, in spectral bands where frequency hopping is used.